Numerous proposals have been made in recent years for mounting a semiconductor IC on a printed circuit board in a bare-chip state in order to satisfy the requirements of smaller size and thinner profile for a semiconductor IC mounting module. A semiconductor IC in a bare-chip state has an extremely narrow electrode pitch compared to a packaged semiconductor IC. Therefore, when a bare-chip semiconductor IC is mounted on a printed circuit board, a critical issue is the manner in which an electrode (hereinafter referred to as a “pad electrode”) provided to a semiconductor IC is connected to wiring (hereinafter referred to as a “wiring pattern”) provided to the printed circuit board.
Wire bonding is known as one method for connecting a pad electrode with a wiring pattern. This method allows a semiconductor IC in a bare-chip state to be packaged with relative ease, but the region in which the semiconductor IC is mounted must be in a different plane on the substrate from the region in which the bonding wire is connected. This method therefore has drawbacks in that the package surface area is enlarged.
Other known methods for connecting a pad electrode to a wiring pattern include a method whereby a flip-chip connection is made between a printed circuit board and a semiconductor IC that is in a bare-chip state. Although the size of the packaging area can be reduced by this method, this method has drawbacks in that a complicated process is involved in creating multiple layers of under barrier metal that must be formed on the surface of the pad electrode in order to adequately maintain the mechanical strength of the connection between the pad electrode and the wiring pattern.
Since both of the methods described above involve mounting a semiconductor IC on the surface of a printed circuit board, the difficulty of reducing the thickness of the module as a whole is a drawback that is common to both methods. Methods for overcoming this drawback are described in Japanese Laid-open Patent Application Nos. H9-321408, 2002-246500, 2001-339165, 2002-50874, 2002-170840, 2002-246507, and 2003-7896. In these methods, a cavity is formed in a printed circuit board, a bare-chip semiconductor IC is embedded in the cavity, and a semiconductor IC-embedded substrate is formed thereby.
However, in the methods described in Japanese Laid-open Patent Application Nos. H9-321408, 2002-246500, 2001-339165, 2002-50874, 2002-170840, 2002-246507, and 2003-7896, the thickness of the printed circuit board must be increased to a certain degree in order to maintain the strength of the portion in which the cavity is formed. This increase in thickness is a drawback in that it interferes with reducing the thickness of the module. Furthermore, since the size of the cavity in its planar direction must be set so as to be somewhat larger than the size of the semiconductor IC in its planar direction, the pad electrode and the wiring pattern become misaligned with each other, and it is therefore extremely difficult to utilize a semiconductor IC that has a narrow electrode pitch of 100 μm or less.
Since each pad electrode is exposed by laser irradiation when a semiconductor IC is embedded, as the electrode pitch of the semiconductor IC becomes narrower, even higher precision is required for the process, and the processing time also increases in proportion to the number of pad electrodes. The diameter of a via formed by laser irradiation must also be reduced as the electrode pitch of the semiconductor IC becomes narrower, and drawbacks therefore occur in that it becomes difficult to perform desmearing of the inside of the via.
However, Japanese Laid-open Patent Application No. 2005-64470 discloses a method whereby semiconductor IC is fixed to a transfer board, and in this state, a post electrode provided to a printed circuit board is inserted in a positioning hole provided to the transfer board. The semiconductor IC is thereby embedded in an uncured or partially cured resin layer, and the pad electrode is then exposed by polishing or blasting. According to this method, not only can a semiconductor IC be positioned with high precision, but it is also possible to overcome the drawbacks described above that occur when each pad electrode is exposed by laser irradiation.
However, the method described in Japanese Laid-open Patent Application No. 2005-64470 has drawbacks in that constraints are imposed by the requirement that a post electrode be formed in advance on the printed circuit board. Since a transfer board must also be manufactured, this method cannot be considered suitable for the manufacture of all semiconductor IC-embedded substrates.
Although not related to methods for manufacturing a semiconductor IC-embedded substrate, examples of methods that use polishing or blasting to uncover an electrode provided to a semiconductor IC are described in Japanese Laid-open Patent Application Nos. H11-274241, 2001-250902, and 2003-197655.